Added SILC Thread Queue API

[silc.git] / lib / silcmath / tma_superclass.h

diff --git a/lib/silcmath/tma_superclass.h b/lib/silcmath/tma_superclass.h
index b50ecb09a8a04997a62852b3c50134c7776d963b..0eeaf5f8745c85253587fb7754bb89eceebfaf9a 100644 (file)
--- a/lib/silcmath/tma_superclass.h
+++ b/lib/silcmath/tma_superclass.h
@@ -4,7 +4,7 @@
 #define LTM_ALL
 
 /* RSA only (does not support DH/DSA/ECC) */
-// #define SC_RSA_1
+/* #define SC_RSA_1 */
 
 /* For reference.... On an Athlon64 optimizing for speed...
 
@@ -60,9 +60,9 @@
    #undef  BN_FAST_MP_INVMOD_C
 
    /* To safely undefine these you have to make sure your RSA key won't exceed the Comba threshold
-    * which is roughly 255 digits [7140 bits for 32-bit machines, 15300 bits for 64-bit machines] 
+    * which is roughly 255 digits [7140 bits for 32-bit machines, 15300 bits for 64-bit machines]
     * which means roughly speaking you can handle upto 2536-bit RSA keys with these defined without
-    * trouble.  
+    * trouble.
     */
    #undef  BN_S_MP_MUL_DIGS_C
    #undef  BN_S_MP_SQR_C
@@ -70,3 +70,7 @@
 #endif
 
 #endif
+
+/* $Source$ */
+/* $Revision$ */
+/* $Date$ */