o Counter block send/receive IV 64 bits instead of 32 bits, and the
value itself is used as 64-bit MSB ordered counter, which must
be reset before the packet sequence counter wraps. It's basically
o Counter block send/receive IV 64 bits instead of 32 bits, and the
value itself is used as 64-bit MSB ordered counter, which must
be reset before the packet sequence counter wraps. It's basically