From ae1b5cd1a06d3556f456ab78ccd014958128e3b1 Mon Sep 17 00:00:00 2001
From: Pekka Riikonen <priikone@silcnet.org>
Date: Sat, 23 Feb 2008 15:39:16 +0200
Subject: [PATCH] Added silc_rolc, silc_rorc, silc_rolc64 and silc_rorc64

---
 configure.ad             |  14 +++---
 lib/silcutil/silctypes.h | 106 +++++++++++++++++++++++++++++++++++++--
 2 files changed, 107 insertions(+), 13 deletions(-)

diff --git a/configure.ad b/configure.ad
index 5b6c9510..c9c292c9 100644
--- a/configure.ad
+++ b/configure.ad
@@ -197,17 +197,15 @@ if test x$want_cpu_optimizations = xtrue; then
   # Set some compiler options based on CPU
   if test "x$CC" = "xicc"; then
     # ICC flags
-    if test x$x_have_cpu_sse2 = xtrue; then
-      SILC_ADD_CFLAGS(-axW)
-    fi
-    if test x$x_have_cpu_sse3 = xtrue; then
-      SILC_ADD_CFLAGS(-axP)
+    if test x$x_have_cpu_sse4 = xtrue; then
+      SILC_ADD_CFLAGS(-axS)
     fi
     if test x$x_have_cpu_ssse3 = xtrue; then
       SILC_ADD_CFLAGS(-axT)
-    fi
-    if test x$x_have_cpu_sse4 = xtrue; then
-      SILC_ADD_CFLAGS(-axS)
+    elif test x$x_have_cpu_pni = xtrue; then
+      SILC_ADD_CFLAGS(-axP)
+    elif test x$x_have_cpu_sse2 = xtrue; then
+      SILC_ADD_CFLAGS(-axW)
     fi
   else
     # Other compilers
diff --git a/lib/silcutil/silctypes.h b/lib/silcutil/silctypes.h
index 8a9c53bc..bd93559b 100644
--- a/lib/silcutil/silctypes.h
+++ b/lib/silcutil/silctypes.h
@@ -821,7 +821,31 @@ static inline SilcUInt32 silc_rol(SilcUInt32 val, int num)
 {
 #if (defined(SILC_I386) || defined(SILC_X86_64)) && defined(__GNUC__)
   asm volatile ("roll %%cl, %0"
-		: "=q" (val) : "0" (val), "c" (num));
+		: "=r" (val) : "0" (val), "c" (num));
+  return val;
+#else
+  return ((val << (SilcUInt32)num) | (val >> (32 - (SilcUInt32)num)));
+#endif /* (SILC_I486 || SILC_X86_64) && __GNUC__ */
+}
+
+/****d* silcutil/silc_rolc
+ *
+ * NAME
+ *
+ *    static inline SilcUInt32 silc_rolc(SilcUInt32 val, const int num);
+ *
+ * DESCRIPTION
+ *
+ *    Rotate 32-bit integer's bits to left `num' times.  Bits pushed to the
+ *    left will appear from the right side of the integer, thus rotating.
+ *    Returns the rotated value.
+ *
+ ***/
+static inline SilcUInt32 silc_rolc(SilcUInt32 val, const int num)
+{
+#if (defined(SILC_I386) || defined(SILC_X86_64)) && defined(__GNUC__)
+  asm volatile ("roll %2, %0"
+		: "=r" (val) : "0" (val), "I" (num));
   return val;
 #else
   return ((val << (SilcUInt32)num) | (val >> (32 - (SilcUInt32)num)));
@@ -845,7 +869,31 @@ static inline SilcUInt32 silc_ror(SilcUInt32 val, int num)
 {
 #if (defined(SILC_I386) || defined(SILC_X86_64)) && defined(__GNUC__)
   asm volatile ("rorl %%cl, %0"
-		: "=q" (val) : "0" (val), "c" (num));
+		: "=r" (val) : "0" (val), "c" (num));
+  return val;
+#else
+  return ((val >> (SilcUInt32)num) | (val << (32 - (SilcUInt32)num)));
+#endif /* (SILC_I486 || SILC_X86_64) && __GNUC__ */
+}
+
+/****d* silcutil/silc_rorc
+ *
+ * NAME
+ *
+ *    static inline SilcUInt32 silc_ror(SilcUInt32 val, const int num);
+ *
+ * DESCRIPTION
+ *
+ *    Rotate 32-bit integer's bits to right `num' times.  Bits pushed to the
+ *    right will appear from the left side of the integer, thus rotating.
+ *    Returns the rotated value.
+ *
+ ***/
+static inline SilcUInt32 silc_rorc(SilcUInt32 val, const int num)
+{
+#if (defined(SILC_I386) || defined(SILC_X86_64)) && defined(__GNUC__)
+  asm volatile ("rorl %2, %0"
+		: "=r" (val) : "0" (val), "I" (num));
   return val;
 #else
   return ((val >> (SilcUInt32)num) | (val << (32 - (SilcUInt32)num)));
@@ -869,7 +917,31 @@ static inline SilcUInt64 silc_rol64(SilcUInt64 val, int num)
 {
 #if defined(SILC_X86_64) && defined(__GNUC__)
   asm volatile ("rolq %%cl, %0"
-		: "=q" (val) : "0" (val), "c" (num));
+		: "=r" (val) : "0" (val), "c" (num));
+  return val;
+#else
+  return ((val << (SilcUInt64)num) | (val >> (64 - (SilcUInt64)num)));
+#endif /* SILC_X86_64 && __GNUC__ */
+}
+
+/****d* silcutil/silc_rolc64
+ *
+ * NAME
+ *
+ *    static inline SilcUInt64 silc_rolc64(SilcUInt64 val, const int num);
+ *
+ * DESCRIPTION
+ *
+ *    Rotate 64-bit integer's bits to left `num' times.  Bits pushed to the
+ *    left will appear from the right side of the integer, thus rotating.
+ *    Returns the rotated value.
+ *
+ ***/
+static inline SilcUInt64 silc_rolc64(SilcUInt64 val, const int num)
+{
+#if defined(SILC_X86_64) && defined(__GNUC__)
+  asm volatile ("rolq %2, %0"
+		: "=r" (val) : "0" (val), "J" (num));
   return val;
 #else
   return ((val << (SilcUInt64)num) | (val >> (64 - (SilcUInt64)num)));
@@ -893,7 +965,31 @@ static inline SilcUInt64 silc_ror64(SilcUInt64 val, int num)
 {
 #if defined(SILC_X86_64) && defined(__GNUC__)
   asm volatile ("rorq %%cl, %0"
-		: "=q" (val) : "0" (val), "c" (num));
+		: "=r" (val) : "0" (val), "c" (num));
+  return val;
+#else
+  return ((val >> (SilcUInt64)num) | (val << (64 - (SilcUInt64)num)));
+#endif /* SILC_X86_64 && __GNUC__ */
+}
+
+/****d* silcutil/silc_rorc64
+ *
+ * NAME
+ *
+ *    static inline SilcUInt64 silc_rorc64(SilcUInt64 val, const int num);
+ *
+ * DESCRIPTION
+ *
+ *    Rotate 64-bit integer's bits to right `num' times.  Bits pushed to the
+ *    right will appear from the left side of the integer, thus rotating.
+ *    Returns the rotated value.
+ *
+ ***/
+static inline SilcUInt64 silc_rorc64(SilcUInt64 val, const int num)
+{
+#if defined(SILC_X86_64) && defined(__GNUC__)
+  asm volatile ("rorq %2, %0"
+		: "=r" (val) : "0" (val), "J" (num));
   return val;
 #else
   return ((val >> (SilcUInt64)num) | (val << (64 - (SilcUInt64)num)));
@@ -931,7 +1027,7 @@ static inline SilcUInt64 silc_ror64(SilcUInt64 val, int num)
  *
  ***/
 #if defined(__GNUC__)
-#define silc_attribute(attrlist) __attribute__(attrlist)
+#define silc_attribute(attrlist) __attribute__ (attrlist)
 #else
 #define silc_attribute(attrlist)
 #endif /* __GNUC__ */
-- 
2.24.0