Added SILC_STR_STRING and SILC_STR_STRING_APPEND and support for

[crypto.git] / lib / silcutil / silctypes.h

diff --git a/lib/silcutil/silctypes.h b/lib/silcutil/silctypes.h
index eff99f17faf081a2730ffc7829cebb98fd13682b..f060a3e08f80e04d1b6a2815b6fb8d8a706d149c 100644 (file)
--- a/lib/silcutil/silctypes.h
+++ b/lib/silcutil/silctypes.h
@@ -4,7 +4,7 @@
 
   Author: Pekka Riikonen <priikone@silcnet.org>
 
-  Copyright (C) 2002 - 2007 Pekka Riikonen
+  Copyright (C) 2002 - 2008 Pekka Riikonen
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
@@ -268,6 +268,53 @@ typedef void * SilcSocket;
 #endif
 /***/
 
+/****d* silcutil/SILCTypes/SilcParam
+ *
+ * NAME
+ *
+ *    typedef SilcUInt32 SilcParam;
+ *
+ * DESCRIPTION
+ *
+ *    A generic parameters that describe the type of an parameter or argument.
+ *    They can be used to describe function arguments, buffer encoding format,
+ *    etc.
+ *
+ * SOURCE
+ */
+typedef SilcUInt32 SilcParam;
+
+#define SILC_PARAM_SINT8         1             /* SilcInt8 */
+#define SILC_PARAM_UINT8         2             /* SilcUInt8 */
+#define SILC_PARAM_SINT16        3             /* SilcInt16 */
+#define SILC_PARAM_UINT16        4             /* SilcUInt16 */
+#define SILC_PARAM_SINT32        5             /* SilcInt32 */
+#define SILC_PARAM_UINT32        6             /* SilcUInt32 */
+#define SILC_PARAM_SINT64        7             /* SilcInt64 */
+#define SILC_PARAM_UINT64        8             /* SilcUInt64 */
+#define SILC_PARAM_SICHAR        9             /* signed char * */
+#define SILC_PARAM_UICHAR        10            /* unsigned char * */
+#define SILC_PARAM_BUFFER        11            /* SilcBuffer */
+#define SILC_PARAM_PTR           12            /* void * */
+#define SILC_PARAM_END           0xfeeefff1     /* End of parameters */
+/***/
+
+/* Internal parameter types, not publicly documented */
+#define SILC_PARAM_UI8_STRING    100           /* String (max len 8-bits) */
+#define SILC_PARAM_UI16_STRING   101           /* String (max len 16-bits) */
+#define SILC_PARAM_UI32_STRING   102           /* String (max len 32-bits) */
+#define SILC_PARAM_UI8_NSTRING   103           /* String (max len 8-bits) */
+#define SILC_PARAM_UI16_NSTRING  104           /* String (max len 16-bits) */
+#define SILC_PARAM_UI32_NSTRING  105           /* String (max len 32-bits) */
+#define SILC_PARAM_OFFSET        106
+#define SILC_PARAM_ADVANCE       107
+#define SILC_PARAM_FUNC          108
+#define SILC_PARAM_REGEX         109
+#define SILC_PARAM_OFFSET_START  110
+#define SILC_PARAM_OFFSET_END    111
+#define SILC_PARAM_APPEND        112
+#define SILC_PARAM_ALLOC         0x00010000     /* Allocate, bitmask */
+
 /* Macros */
 
 #if (defined(SILC_I486) || defined(SILC_X86_64)) && defined(__GNUC__)
@@ -846,7 +893,7 @@ static inline SilcUInt64 silc_ror64(SilcUInt64 val, int num)
  *
  * DESCRIPTION
  *
- *    Brach prediction macro.  It specifies that it is likely that the brach
+ *    Branch prediction macro.  It specifies that it is likely that the branch
  *    where silc_likely is applied is taken.  Compiler will optimize the
  *    code based on this prediction.  Never use this before you have profiled
  *    the code first.
@@ -861,10 +908,10 @@ static inline SilcUInt64 silc_ror64(SilcUInt64 val, int num)
  *
  * DESCRIPTION
  *
- *    Brach prediction macro.  It specifies that it is unlikely that the brach
- *    where silc_unlikely is applied is taken.  Compiler will optimize the
- *    code based on this prediction.  Never use this before you have profiled
- *    the code first.
+ *    Branch prediction macro.  It specifies that it is unlikely that the
+ *    branch where silc_unlikely is applied is taken.  Compiler will optimize
+ *    the code based on this prediction.  Never use this before you have
+ *    profiled the code first.
  *
  ***/
 #if __GNUC__ >= 3
@@ -924,24 +971,24 @@ void silc_prefetch(void *addr, int rw, int locality)
  *    Enforced block prefetch.  This function loads the specified amount
  *    `prefetch_length' of memory from the specified address `addr' to CPU
  *    cache with each loaded cache line being the size of `cache_line_length'.
- *    If you don't know the cache line size use 32 bytes.  Note that, the
+ *    If you don't know the cache line size use 64 bytes.  Note that, the
  *    `cache_line_length' is a const int.  In this context this mean its
  *    value must not come from a variable but must be a constant (the code
  *    won't compile if it comes from a variable).
  *
  *    The `prefetch_length' must be multiple of twice of the
- *    `cache_line_length' or 64 if you don't know the cache line size, hence
- *    the minimum length for `prefetch_length' is 64 bytes when the
- *    `cache_line_length' is 32 bytes.
+ *    `cache_line_length' or 128 if you don't know the cache line size, hence
+ *    the minimum length for `prefetch_length' is 128 bytes when the
+ *    `cache_line_length' is 64 bytes.  Shorter cache line length (32 bytes)
+ *    can be used too.
  *
  *    You should use the correct `cache_line_length' value for your CPU or
  *    the value of the CPU for which you want to optimize your code.  Intel
- *    CPUs usually have cache size of 32 or 64 bytes, or both when there are
- *    multiple caches.  The most optimal prefetch is achieved if the
- *    `cache_line_length' is the actual CPU cache line size.  Always do
- *    performance testing with and without prefetching to make sure the
- *    prefetch actually helps.  If used improperly, it may slow down your
- *    program.
+ *    CPUs usually have cache size of 32 or 64 bytes.  The most optimal
+ *    prefetch is achieved if the `cache_line_length' is the actual CPU cache
+ *    line size.  Always do performance testing with and without prefetching
+ *    to make sure the prefetch actually helps.  If used improperly, it may
+ *    slow down your program.
  *
  *    The difference to silc_prefetch is that this function always performs
  *    the prefetch and has the ability to prefetch more than one cache line